Title :
Methodology for 3-dimensional high-density capacitor reliability evaluation
Author :
Fiannaca, G. ; Gardes, P. ; Berneux, L. ; Bouyssou, E. ; Anceau, C.
Author_Institution :
STMicroelectronics, Tours, France
Abstract :
Wafer level accelerated testing is a key tool to perform fast reliability assessment of new technologies. This paper presents an innovative methodology developed to perform accurate life-time extrapolation of 3-dimensional (3D) high density capacitors through constant electric field stress (CES) test. This methodology is first based on dielectric thickness extraction from planar capacitor measurements. CES tests are then performed on 3D capacitors, adjusting the voltage stress with respect to the local dielectric thickness previously extracted. The efficiency of the methodology is demonstrated through constant voltage stress (CVS) and CES test results comparison.
Keywords :
capacitors; dielectric thin films; extrapolation; life testing; semiconductor device reliability; semiconductor device testing; wafer level packaging; 3D high density capacitor; constant electric field stress test; constant voltage stress test; dielectric thickness extraction; fast reliability assessment; life-time extrapolation; three dimensional high-density capacitor reliability; wafer level accelerated testing; Capacitors; Costs; Dielectric measurements; Electrodes; Extrapolation; Life estimation; Life testing; Performance evaluation; Stress; Voltage;
Conference_Titel :
Integrated Reliability Workshop Final Report, 2009. IRW '09. IEEE International
Conference_Location :
S. Lake Tahoe, CA
Print_ISBN :
978-1-4244-3921-8
Electronic_ISBN :
1930-8841
DOI :
10.1109/IRWS.2009.5383017