Hardware-Software Co-Synthesis of Heterogeneous Embedded Computer Systems

Hardware-software co-synthesis of embedded computer systems involves the partitioning of a system specification into hardware and software modules to meet various system requirements. High-performance embedded computers typically incorporate heterogeneous multiple processing elements. In this paper, we present an approach to co-synthesis of high performance embedded systems targeting fault tolerant topologies. Our approach supports the following features: 1) input in the form of an acyclic periodic task graph with real-time constraints, 2) pipelining of task graphs, 3) use of a heterogeneous set of processing elements, 4) fault tolerance by a newly developed group based fault tolerance technique. We attempt to minimize the communication overhead while preserving regular topology computer systems