Title :
A Fault Simulator for MOS LSI Circuits
Author :
Bose, A.K. ; Kozak, P. ; Lo, C.-Y. ; Nham, H.N. ; Pacas-Skewes, E. ; Wu, K.
Author_Institution :
Bell Laboratories, Murray Hill, NJ
Abstract :
This paper describes a fault simulator for MOS LSI circuits. The basic primitives for this simulator are MOS transistor structures where the transistors are evaluated logically. The simulator provides the capability of modeling and simulating both the classical input/output stuck-at faults and the non-classical transistor stuck-on and stuck-open faults.
Keywords :
Analytical models; Circuit faults; Circuit simulation; Computational modeling; Large scale integration; Logic circuits; Logic devices; Logic gates; MOS devices; MOSFETs;
Conference_Titel :
Design Automation, 1982. 19th Conference on
Conference_Location :
Las Vegas, NV, USA
Print_ISBN :
0-89791-020-6
DOI :
10.1109/DAC.1982.1585530
