Design and implementation of low-power DCT chip for portable multimedia terminals

This paper describes the design and implementation of a low power 2D DCT chip for portable multimedia terminals. The chip architecture based on direct 2D approach reduces computational complexity and the power dissipation can be reduced accordingly. In the implementation of the direct 2D algorithm, a parallel distributed arithmetic (DA) architecture at reduced supply voltage is adopted. In the real circuit implementation of the chip, an adder of low power consumption is designed, as well as a power-saving ROM and a low-voltage two-port SRAM with sequential access. The resultant 2D DCT chip is realized by 0.6 μm single-poly double-metal technology. Critical path simulation indicates a maximum input rate of 133 MHz, and it consumes 138 mW at 100 MHz. The measured chip speed is around 100 MHz