Title :
An Enhancement of LSSD to Reduce Test Pattern Generation Effort and Increase Fault Coverage
Author :
Saluja, Kewal K.
Author_Institution :
University of Newcastle
Abstract :
In this paper we propose designs of latches which can be used in Level Sensitive Scan Design NLSSD). These new designs can use the existing software support for design rule checks but result into a reduction of effort in test pattern generation and provide a better fault coverage. The system performance is not degraded with the use of latches proposed in this paper.
Keywords :
Circuit testing; Clocks; Combinational circuits; Computer aided manufacturing; Design engineering; Design for testability; Latches; Logic; Reliability engineering; Test pattern generators;
Conference_Titel :
Design Automation, 1982. 19th Conference on
Conference_Location :
Las Vegas, NV, USA
Print_ISBN :
0-89791-020-6
DOI :
10.1109/DAC.1982.1585543
