Parallel no-waiting pipelining accelerating CT image reconstruction based on FPGA

On the research of applied three-dimensional computed tomography (CT) image reconstruction, the high-performance computing problem has always been one of the difficulties and hotspots. As a sort of hardware executed parallel in space domain and reconstructed in time domain, FPGA has developed rapidly in recent years. It has been widely used as high-performance parallel computing accelerating component. In this paper, the problem of accelerating the classical three-dimensional image reconstruction algorithm FDK with FPGA was studied. Then, the new accelerating method which was called parallel no-waiting pipelining was proposed. The experimental results showed that the method obtained a considerable speedup, and had the characteristics of resources optimization. The method may be taken as the useful reference for researchers working on FPGA applications and high-performance applications.