Developments in Logic Network Path Delay Analysis

This paper discusses path delay analysis programs as an alternative to detailed logic simulation for finding timing problems in logic networks. Fundamentals of path delay analysis are reviewed, and several previously reported methods are surveyed. This is followed by a more detailed description of a delay analysis program that we have recently implemented. Our implementation uncovers a wide variety of timing problems and has a run time that is linearly proportional to the number of gates in the network. Other principle features are that timing information loss is minimized by treating 0-to-1 and 1-to-0 delays separately, and the user is given the capability of selectively disabling paths in order to discover timing problems that would otherwise remain hidden.