• DocumentCode
    3144724
  • Title

    Timing Verification System Based on Delay Time Hierarchical Nature

  • Author

    Nomura, Minoru ; Sato, Shinichi ; Takano, Nobuo ; Aoyama, Toshinori ; Yamada, Akihiko

  • Author_Institution
    Nippon Electric Co., Ltd., Tokyo, JAPAN
  • fYear
    1982
  • fDate
    14-16 June 1982
  • Firstpage
    622
  • Lastpage
    628
  • Abstract
    A hierarchical timing verification system is described. It can evaluate all logical paths in a chip without any specific manual input information, using a path tracing algorithm. This hierarchical approach can drastically reduce the number of logical paths to be traced and the corresponding computation time. This system is used for designing master slice (gate array) LSIs and building block LSIs.
  • Keywords
    Analytical models; Circuit simulation; Cities and towns; Computational modeling; Delay effects; Delay systems; Digital circuits; Fabrication; SPICE; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation, 1982. 19th Conference on
  • Conference_Location
    Las Vegas, NV, USA
  • ISSN
    0146-7123
  • Print_ISBN
    0-89791-020-6
  • Type

    conf

  • DOI
    10.1109/DAC.1982.1585561
  • Filename
    1585561
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3144724