Title :
A 16-bit parallel MAC architecture for a multimedia RISC processor
Author :
Kuroda, Ichiro ; Murata, Eri ; Nadehara, Kouhei ; Suzuki, Kazumasa ; Arai, Tomohisa ; Okamura, Atsushi
Author_Institution :
NEC Corp., Kawasaki, Japan
Abstract :
This paper presents a parallel MAC (multiply-accumulation) architecture designed for DSP applications on a 200-MHz, 1.6-GOPS multimedia RISC processor. The datapath architecture of the processor is designed to realize parallel execution of a data transfer and SIMD parallel arithmetic operations. SIMD parallel 16-bit MAC instructions are introduced with a symmetric rounding scheme which maximizes the accuracy of the 18-bit accumulation. This parallel 16-bit MAC instruction on a 64-bit datapath is shown to be efficiently utilized for DSP applications such as convolution in the multimedia RISC processor. By using the parallel MAC instruction with the symmetric rounding scheme, the two-dimensional inverse discrete cosine transform (2D-IDCT) which satisfies IEEE 1180 can be implemented in 202 cycles
Keywords :
convolution; digital arithmetic; digital signal processing chips; discrete cosine transforms; multimedia systems; parallel architectures; reduced instruction set computing; 16 bit; 200 MHz; 2D-IDCT; DSP applications; IEEE 1180; SIMD; convolution; data transfer; datapath architecture; multimedia RISC processor; multiply-accumulation architecture; parallel MAC architecture; parallel arithmetic operations; symmetric rounding scheme; two-dimensional inverse discrete cosine transform; Application software; Arithmetic; Convolution; Digital signal processing; Discrete cosine transforms; Laboratories; Microcomputers; Microprocessors; National electric code; Process design; Reduced instruction set computing; Silicon;
Conference_Titel :
Signal Processing Systems, 1998. SIPS 98. 1998 IEEE Workshop on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-7803-4997-0
DOI :
10.1109/SIPS.1998.715773
