DocumentCode
3145046
Title
Arbitrarily-Sized Module Location Technique in the LOP System
Author
Odawara, Gotaro ; Iijima, Kazuhiko ; Kiyomatsu, Tetsuro
Author_Institution
University of Tokyo, Tokyo, Japan
fYear
1982
fDate
14-16 June 1982
Firstpage
718
Lastpage
726
Abstract
This paper describes a new location technique in the LOcation Processor (LOP), which is an automatic module location system for PWB. This technique consists of two items: one is the advanced algorithm for arbitrarily-sized and -shaped module location, and the other is the empirical path-anticipation method in the location optimization. Several experiments have proven the effectiveness of this technique, and have suggested a new approach to the automatic layout system for PWB and LSI.
Keywords
Circuit synthesis; Circuit testing; Design automation; Inspection; Logic circuits; Logic devices; Packaging; Process design; Routing; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation, 1982. 19th Conference on
Conference_Location
Las Vegas, NV, USA
ISSN
0146-7123
Print_ISBN
0-89791-020-6
Type
conf
DOI
10.1109/DAC.1982.1585575
Filename
1585575
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