A 12-bit 100-MS/s pipelined ADC in 45-nm CMOS

This paper presents a 12-bit 100-MS/s pipeline analog-to-digital converter (ADC) in a 45-nm CMOS technology. The low-voltage circuit techniques and a careful layout are adopted to obtain high-resolution in a low-supply. The ADC features 12-bit resolution, 100-MS/s sampling rate, differential nonlinearity (DNL) of ±0.58 LSB, integral nonlinearity (INL) of ±2.79 LSB, and power consumption of 30.4 mW. With a sampling frequency of a 100-MS/s and an input of a 2.4 MHz, the ADC achieves a signal to noise-and-distortion ratio and a spurious-free dynamic range of 59.02 dB and 63.22 dB, at a supply voltage of 1.1 V, respectively.