• DocumentCode
    3145150
  • Title

    Analysis of SRAM hierarchical bitlines for optimal performance and variation tolerance

  • Author

    Li, Qi ; Kim, Tony T.

  • Author_Institution
    Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore, Singapore
  • fYear
    2011
  • fDate
    17-18 Nov. 2011
  • Firstpage
    412
  • Lastpage
    415
  • Abstract
    Hierarchical bitlines improve performance and power consumption due to the reduced bitline capacitance associated with read/write operations. This paper analyzes hierarchical bitlines and provides optimal solutions for maximum performance and minimum variance. Simulation results demonstrate that the optimized 2-stage hierarchical bitlines in the conventional 6T and 8T SRAMs improve the performance by 41.5% and 63.8%, and the performance variance (σ2) by 65.7% and 88.0%.
  • Keywords
    SRAM chips; low-power electronics; SRAM hierarchical bitlines; memory size 6 TByte; memory size 8 TByte; optimal performance; optimized 2-stage hierarchical bitlines; power consumption; read-write operation; variation tolerance; Circuit optimization; Hierarchical bitlines; Static random access memory (SRAM); Variation tolerant design;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SoC Design Conference (ISOCC), 2011 International
  • Conference_Location
    Jeju
  • Print_ISBN
    978-1-4577-0709-4
  • Electronic_ISBN
    978-1-4577-0710-0
  • Type

    conf

  • DOI
    10.1109/ISOCC.2011.6138619
  • Filename
    6138619
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3145150