DocumentCode :
314518
Title :
A non-deterministic scheduling and allocation model for mapping algorithms on configurable architectures
Author :
Nemer, Elias ; Goubran, Rafik ; Mahmoud, Samy
Author_Institution :
Nortel, Verdun, Que., Canada
Volume :
1
fYear :
1997
fDate :
25-28 May 1997
Firstpage :
19
Abstract :
Mapping an algorithm on a configurable architecture containing several types of function units requires an efficient allocation of the available computational resources to the various operations in order to exploit the parallelism and minimize the execution time. This resource scheduling/allocation problem consists of determining when and on which unit to schedule a given task with the objective of minimizing total execution time, while respecting precedence relations and resource constraints. In this paper, we use a branch and bound search method with a non deterministic heuristic to find quasi optimal solution to the allocation problem. Partial schedules are built up starting at time 0 and proceed systematically by adding at each decision point subsets of activities until a complete feasible schedule is obtained. At each decision point m, the procedure identifies all operations that can be put in progress according to precedence rules. If it is impossible to schedule all eligible activities at time m, a heuristic is used to determine which operations are to be scheduled and which are to be delayed. The key idea of the heuristic is that, given the set of available resources (AR) and the set of candidate operations (SC) that meet precedence constraints, the criteria for matching operation j with resource k is a probabilistic decision based on quantifying the opportunity cost of k and the scheduling urgency of j
Keywords :
parallel architectures; processor scheduling; reconfigurable architectures; resource allocation; allocation model; allocation problem; branch and bound search method; configurable architectures; mapping algorithms; non deterministic heuristic; non-deterministic scheduling; Business; Computer architecture; Concurrent computing; Costs; Flow graphs; Hardware; Parallel processing; Processor scheduling; Resource management; Scheduling algorithm;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electrical and Computer Engineering, 1997. Engineering Innovation: Voyage of Discovery. IEEE 1997 Canadian Conference on
Conference_Location :
St. Johns, Nfld.
ISSN :
0840-7789
Print_ISBN :
0-7803-3716-6
Type :
conf
DOI :
10.1109/CCECE.1997.614779
Filename :
614779
Link To Document :
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