Rapid prototyping of modular/hypercube trellis decoders for communication systems

Author

Pouliot, L.E. ; Fortier, P.

Author_Institution

Dept. of Electr. & Comput. Eng., Laval Univ., Sainte-Foy, Que., Canada

Volume

1

fYear

1997

fDate

25-28 May 1997

Firstpage

83

Abstract

In this work, we look at a novel approach for the realization of a fully parallel decoder based on the Viterbi algorithm and hypercube architecture using a rapid prototyping method on FPGAs. Our proposed modular/hypercube architecture allows optimization of the surface by connecting modules together in such a way that a minimum of interconnections between modules is needed. Further optimization is possible using temporal multiplexing

Keywords

Viterbi decoding; convolutional codes; digital communication; field programmable gate arrays; hypercube networks; multichip modules; optimisation; parallel architectures; software prototyping; trellis codes; FPGA; Viterbi algorithm; communication systems; convolutional codes; fully parallel decoder; modular/hypercube architecture; optimization; rapid prototyping; temporal multiplexing; trellis decoders; Computer architecture; Convolutional codes; Decoding; Digital communication; Field programmable gate arrays; Hypercubes; Joining processes; Prototypes; Registers; Viterbi algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Computer Engineering, 1997. Engineering Innovation: Voyage of Discovery. IEEE 1997 Canadian Conference on

Conference_Location

St. Johns, Nfld.

ISSN

0840-7789

Print_ISBN

0-7803-3716-6

Type

conf

DOI

10.1109/CCECE.1997.614795

Filename

614795