DocumentCode
3145286
Title
A formal method for computer design verification
Author
Pitchumani, Vijay ; Stabler, Edward P.
Author_Institution
Syracuse University, Syracuse, NY
fYear
1982
fDate
14-16 June 1982
Firstpage
809
Lastpage
814
Abstract
A formal computer design verification method based on Floyd´s inductive assertion technique[9] is presented as an alternative or at least a supplement to simulation. The semantics of a register transfer language is defined formally. It specifies how machine variables and time change. Hardware descriptions in this language may contain assertions. The formal definition of the language can then be used for automatic verification of logical correctness and realtime performance of the design.
Keywords
Computational modeling; Computer simulation; Design engineering; Design methodology; Formal verification; Hardware; Logic design; Registers; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation, 1982. 19th Conference on
Conference_Location
Las Vegas, NV, USA
ISSN
0146-7123
Print_ISBN
0-89791-020-6
Type
conf
DOI
10.1109/DAC.1982.1585588
Filename
1585588
Link To Document