Title :
Toolchain for Programming, Simulating and Studying the XMT Many-Core Architecture
Author :
Keceli, Fuat ; Tzannes, Alexandros ; Caragea, George C. ; Barua, Rajeev ; Vishkin, Uzi
Author_Institution :
Univ. of Maryland, College Park, MD, USA
Abstract :
The Explicit Multi-Threading (XMT) is a general-purpose many-core computing platform, with the vision of a 1000-core chip that is easy to program but does not compromise on performance. This paper presents a publicly available tool chain for XMT, complete with a highly configurable cycle-accurate simulator and an optimizing compiler. The XMT tool chain has matured and has been validated to a point where its description merits publication. In particular, research and experimentation enabled by the tool chain played a central role in supporting the ease-of-programming and performance aspects of the XMT architecture. The compiler and the simulator are also important milestones for an efficient programmer´s workflow from PRAM algorithms to programs that run on the shared memory XMT hardware. This workflow is a key component in accomplishing the dual goal of ease-of-programming and performance. The applicability of our tool chain extends beyond specific XMT choices. It can be used to explore the much greater design space of shared memory many-cores by system researchers or by programmers. As the tool chain can practically run on any computer, it provides a supportive environment for teaching parallel algorithmic thinking with a programming component. Unobstructed by techniques such as decomposition-first and programming for locality, this environment may be useful in deferring the teaching of these techniques, when desired, to more advanced or platform-specific courses.
Keywords :
concurrency theory; multi-threading; optimising compilers; parallel architectures; shared memory systems; PRAM algorithm; XMT architecture; XMT many-core architecture; XMT tool chain; cycle-accurate simulator; ease-of-programming; explicit multithreading; general-purpose many-core computing; optimizing compiler; programmer workflow; programming component; shared memory XMT hardware; shared memory many-core; Algorithm design and analysis; Assembly; Computer architecture; Parallel processing; Phase change random access memory; Program processors; Programming;
Conference_Titel :
Parallel and Distributed Processing Workshops and Phd Forum (IPDPSW), 2011 IEEE International Symposium on
Conference_Location :
Shanghai
Print_ISBN :
978-1-61284-425-1
Electronic_ISBN :
1530-2075
DOI :
10.1109/IPDPS.2011.270