Dual band offset mixer for on-chip RF test in 0.13 μm CMOS

Author

Mehdi, Ghulam

Author_Institution

Centre for Wireless Commun., CESAT, Islamabad, Pakistan

fYear

2009

fDate

14-15 Dec. 2009

Firstpage

1

Lastpage

6

Abstract

This paper discusses motivation and design of an offset mixer and investigates its optimum placement in loopback test setup for on-chip RF test. Based on this study, design and implementation of an offset mixer for on-chip RF testing of radio front ends is presented. The offset mixer is passive in nature reducing silicon area and power overheads. Mixer is implemented in 0.13 μm CMOS process and the design aims for dual band operation i.e. Bluetooth & WLAN standards and high linearity. Post layout results indicate that the mixer has excellent noise figure of 5 dB, low conversion loss of less than 5 dB as well as high IP3 of 12.5 dBm. Proposed passive offset mixer with almost zero dc power consumption and minimal silicon area makes it best suitable for on chip RF test. Pre & post-layout simulation results obtained with Cadence Spectre RF are presented.

Keywords

CMOS integrated circuits; MMIC mixers; elemental semiconductors; field effect MMIC; integrated circuit layout; integrated circuit modelling; integrated circuit noise; integrated circuit testing; losses; silicon; Bluetooth standard; CMOS process; Cadence Spectre RF; IP3 value; Si; WLAN standard; conversion loss; dual band offset mixer design; loopback test setup; noise figure; on-chip RF test; passive offset mixer; post-layout simulation; power overhead; radio front end; silicon area; size 0.13 μm; CMOS; Key words; Noise Figure; RF; loopback; offset mixer;

fLanguage

English

Publisher

ieee

Conference_Titel

Multitopic Conference, 2009. INMIC 2009. IEEE 13th International

Conference_Location

Islamabad

Print_ISBN

978-1-4244-4872-2

Electronic_ISBN

978-1-4244-4873-9

Type

conf

DOI

10.1109/INMIC.2009.5383099

Filename

5383099