DocumentCode :
3145347
Title :
A Verification Technique for Hardware Designs
Author :
Maruyama, Fumihiro ; Uehara, Takao ; Kawato, Nobuaki ; Saito, Takao
Author_Institution :
Software Laboratory FUJITSU Laboratories Ltd., Kawasaki, Japan
fYear :
1982
fDate :
14-16 June 1982
Firstpage :
832
Lastpage :
841
Abstract :
Most existing hardware design verification techniques (logic simulation, symbolic simulation etc.), as well as the design phase, are rather synthetic. This paper discusses an analytic verification technique with examples of its application. This technique employs backward symbolic simuation, or causality tracing, which is carried out from the negation of a proposition which should be verified. Analyticity this technique has, not only makes verification powerful but gives it another feature, design error diagnosis.
Keywords :
Application software; Automata; Computer errors; Digital systems; Hardware; Laboratories; Logic design; Power engineering computing; Power system reliability; Registers;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation, 1982. 19th Conference on
Conference_Location :
Las Vegas, NV, USA
ISSN :
0146-7123
Print_ISBN :
0-89791-020-6
Type :
conf
DOI :
10.1109/DAC.1982.1585591
Filename :
1585591
Link To Document :
بازگشت