Evaluation of 1´s complement arithmetic for the implementation low power CMOS floating point adders

In CMOS logic implementations, the architecture of functional units reflects the algorithmic cause effect relations as far as logic functionality, structural complexity, power consumption and speed of operation are concerned. The paper addresses the architectural evaluation of arithmetic units based on 1´s complement algorithms for the implementation of low power floating point units. Our investigations suggest the suitability of 1´s complement adders for the realization of low power floating point adders/subtracters, accumulators and multiply accumulators. The power consumption and silicon area of 1´s complement adders that realize functions of the type |A-B| involving integer data A and B, are around 50% of that of their 2´s complement counterparts