Title :
Evaluation of 1´s complement arithmetic for the implementation low power CMOS floating point adders
Author :
Pillai, R.V.K. ; Al-Khalili, D. ; Al-Khalili, AJ
Author_Institution :
Concordia Univ., Montreal, Que., Canada
Abstract :
In CMOS logic implementations, the architecture of functional units reflects the algorithmic cause effect relations as far as logic functionality, structural complexity, power consumption and speed of operation are concerned. The paper addresses the architectural evaluation of arithmetic units based on 1´s complement algorithms for the implementation of low power floating point units. Our investigations suggest the suitability of 1´s complement adders for the realization of low power floating point adders/subtracters, accumulators and multiply accumulators. The power consumption and silicon area of 1´s complement adders that realize functions of the type |A-B| involving integer data A and B, are around 50% of that of their 2´s complement counterparts
Keywords :
CMOS logic circuits; adders; floating point arithmetic; power consumption; 1s complement arithmetic; 2s complement counterparts; CMOS logic implementations; algorithmic cause effect relations; architectural evaluation; arithmetic units; functional units; integer data; logic functionality; low power CMOS floating point adders; low power floating point adders/subtracters; low power floating point units; multiply accumulators; power consumption; silicon area; structural complexity; Algorithm design and analysis; Bismuth; CMOS logic circuits; Data conversion; Educational institutions; Energy consumption; Floating-point arithmetic; Logic design; Power demand; Silicon;
Conference_Titel :
Electrical and Computer Engineering, 1997. Engineering Innovation: Voyage of Discovery. IEEE 1997 Canadian Conference on
Conference_Location :
St. Johns, Nfld.
Print_ISBN :
0-7803-3716-6
DOI :
10.1109/CCECE.1997.614813
