Considerations on system-level behavioural and structural modeling extensions to VHDL

This paper reviews the requirements on a language for modeling behaviour and structure at the system level, and considers possible approaches to extending VHDL to meet these requirements. Modeling issues in a system-level design language are identified, including abstraction of data, concurrency, communication and timing, and design refinement. Some system-level design languages and notations are surveyed, and previous proposals to extend VHDL for system-level design are reviewed. Specific language design issues for extending VHDL are discussed, and some alternative solutions are presented