Test Generation for Scan Design Circuits with Tri-State Modules and Bidirectional Terminals

This paper describes a program which generates test patterns for scan design circuits with tri-state modules and bidirectional terminals. The test generation procedure uses a path sensitization technique with 14 signal values. The principal features of this program are test generation with automatic decision of I/O mode of bidirectional terminals, generation of test sets for high impedance state, and generation of test sets for system clock control circuits of shift register latches (SRLs) by using shift-in function of SRLs.