DocumentCode
3146033
Title
Guidelines for safe simulation and synthesis of implicit style Verilog
Author
Arnold, Mark G. ; Sample, Neal J. ; Shuler, James D.
Author_Institution
Dept. of Comput. Sci., Wyoming Univ., Laramie, WY, USA
fYear
1998
fDate
16-19 Mar 1998
Firstpage
59
Lastpage
66
Abstract
We discuss the classes of machines for which implicit style design is appropriate, and give guidelines for safe simulation and synthesis of implicit style Verilog that ensure the results of cycle based simulation agree with the results of synthesis. We also propose a minor revision to IEEE 1364 for bottom testing loops that improves the clarity of safe implicit style Verilog
Keywords
IEEE standards; digital simulation; hardware description languages; logic CAD; logic testing; IEEE 1364; Verilog simulation; bottom testing loops; cycle based simulation; implicit style Verilog synthesis; implicit style design; logic CAD; Algorithm design and analysis; Clocks; Computational modeling; Computer science; Computer simulation; Guidelines; Hardware design languages; Scheduling algorithm; Software design; Space exploration;
fLanguage
English
Publisher
ieee
Conference_Titel
Verilog HDL Conference and VHDL International Users Forum, 1998. IVC/VIUF. Proceedings., 1998 International
Conference_Location
Santa Clara, CA
ISSN
1085-9403
Print_ISBN
0-8186-8415-1
Type
conf
DOI
10.1109/IVC.1998.660681
Filename
660681
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