Title :
Guidelines for safe simulation and synthesis of implicit style Verilog
Author :
Arnold, Mark G. ; Sample, Neal J. ; Shuler, James D.
Author_Institution :
Dept. of Comput. Sci., Wyoming Univ., Laramie, WY, USA
Abstract :
We discuss the classes of machines for which implicit style design is appropriate, and give guidelines for safe simulation and synthesis of implicit style Verilog that ensure the results of cycle based simulation agree with the results of synthesis. We also propose a minor revision to IEEE 1364 for bottom testing loops that improves the clarity of safe implicit style Verilog
Keywords :
IEEE standards; digital simulation; hardware description languages; logic CAD; logic testing; IEEE 1364; Verilog simulation; bottom testing loops; cycle based simulation; implicit style Verilog synthesis; implicit style design; logic CAD; Algorithm design and analysis; Clocks; Computational modeling; Computer science; Computer simulation; Guidelines; Hardware design languages; Scheduling algorithm; Software design; Space exploration;
Conference_Titel :
Verilog HDL Conference and VHDL International Users Forum, 1998. IVC/VIUF. Proceedings., 1998 International
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-8186-8415-1
DOI :
10.1109/IVC.1998.660681
