Title :
A neural network based VLSI vector quantizer for real-time image compression
Author :
Fang, Wai-Chi ; Sheu, Bing J. ; Chen, Oscal T -C
Author_Institution :
Dept. of Electr. Eng., Signal & Image Process. Inst., Univ. of Southern California, Los Angeles, CA, USA
Abstract :
A trainable VLSI neuroprocessor for adaptive vector quantization based upon the frequency-sensitive competitive learning algorithm has been developed for high-speed high-ratio image compression applications. Simulation results show that such an algorithm is capable of producing good-quality reconstructed image at compression ratios of more than 20. This design includes a fully parallel vector quantizer and a pipelined codebook generator which obtains a time complexity O(1) for each quantization vector. A 5×5-dimensional vector quantizer prototype chip has been designed, fabricated and tested. It contains 64 inner-product neural units and an extendable winner-take-all block. This mixed-signal chip occupies a compact Si area of 4.6×6.8 mm2 in 2.0-μm scalable CMOS technology
Keywords :
CMOS integrated circuits; VLSI; computational complexity; computerised picture processing; data compression; digital signal processing chips; learning systems; neural nets; parallel processing; pipeline processing; real-time systems; CMOS technology; adaptive vector quantization; chip; compression ratios; design; extendable winner-take-all block; frequency-sensitive competitive learning algorithm; inner-product neural units; pipelined codebook generator; real-time image compression; time complexity; trainable VLSI neuroprocessor; CMOS technology; Data compression; Frequency; Image coding; Image reconstruction; Neural networks; Power capacitors; Speech coding; Vector quantization; Very large scale integration;
Conference_Titel :
Data Compression Conference, 1991. DCC '91.
Conference_Location :
Snowbird, UT
Print_ISBN :
0-8186-9202-2
DOI :
10.1109/DCC.1991.213346
