Title :
TSV fault-tolerant mechanisms with application to 3D clock networks
Author :
Lung, Chiao-Ling ; Chien, Jui-Hung ; Shi, Yiyu ; Chang, Shih-Chieh
Author_Institution :
Dept. of Comput. Sci., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Abstract :
Three-dimensional integrated circuit (3D IC) has become an emerging technology in view of its advantages in packing density and flexibility in heterogeneous integration. Through Silicon Via (TSV) formation is one of the key enabling technologies for 3D ICs. While TSVs provide vertical connections between different dies for higher performance, they suffer from random open defects and thermo-mechanical stress. The potential yield loss can significantly increase the mass production cost, which in turn affects the profitability of 3D ICs. To address the TSV reliability issues, double TSV, shared spare TSV and TSV fault tolerant unit (TFU) techniques have been developed. In this paper, we briefly review them and use 3D clock networks as a vehicle to compare their effectiveness and overhead.
Keywords :
clocks; fault tolerance; integrated circuit reliability; integrated circuit yield; three-dimensional integrated circuits; 3D IC; 3D clock networks; Si; TSV fault-tolerant mechanisms; TSV reliability; double TSV; heterogeneous integration; mass production cost; packing density; packing flexibility; random open defects; shared spare TSV; thermomechanical stress; three-dimensional integrated circuit; through silicon via; vertical connections; yield loss; 3D IC; Clock Network; Clock Tree Synthesis; Double TSV; Fault-tolerant; Redundant Tree; Shared Spare TSV; Through-Silicon Via;
Conference_Titel :
SoC Design Conference (ISOCC), 2011 International
Conference_Location :
Jeju
Print_ISBN :
978-1-4577-0709-4
Electronic_ISBN :
978-1-4577-0710-0
DOI :
10.1109/ISOCC.2011.6138663
