Title :
Process-level modeling with VHDL
Author_Institution :
Bradley Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
Abstract :
The author presents an approach to process-level modeling. Behavioral models are represented using the Process Model Graph (PMG) notation, which dictates a structured approach to model development. Because constituent processes are retrieved from a process primitive library, the system provides for code reuse at the process level and rapid model development. Super nodes are used to represent complicated PMGs in high level graphs. This approach has been implemented in a tool, the Modeler´s Assistant, which has also been a useful framework for behavioral test generation, timing insertion, and natural language interfaces
Keywords :
VLSI; data flow graphs; hardware description languages; logic CAD; Modeler´s Assistant; VHDL; behavioral test generation; constituent processes; natural language interfaces; process model graph notation; process primitive library; process-level modeling; timing insertion; Automatic testing; Circuit synthesis; Circuit testing; Digital signal processing; Graphics; Natural languages; Read only memory; Signal processing; Timing; Very large scale integration;
Conference_Titel :
Verilog HDL Conference and VHDL International Users Forum, 1998. IVC/VIUF. Proceedings., 1998 International
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-8186-8415-1
DOI :
10.1109/IVC.1998.660683
