TSV density-driven global placement for 3D stacked ICs

Via-first through-silicon vias (TSVs) are manufactured through bulk silicon and connected to landing pads in metal layers. Landing pads are made large enough to cover the top surface of TSVs entirely so that TSV-to-landing pad connections become invulnerable to uncertainties such as misalignment between TSVs and landing pads. Large landing pads, however, could lead to metal density mismatch problems, which result in nonuniform topography. In this paper, we investigate the metal density mismatch problem in 3D ICs and propose a TSV density-driven 3D global placement algorithm to minimize topography variation in 3D IC layouts. The experimental results show that we achieve 1.86× improvement in the range of metal 1 densities and 2.10× improvement in the maximum metal 1 density gradient with just 2.3% wirelength overhead. We also present additional studies such as the impact of landing pad size on metal density.