Overcoming the limitations of self-checking stimulus through the use of an ASIC mirror

One of the greatest challenges of verification is the handling of concurrency in a system. A good example of this concurrency is the CPU-to-memory bridge within a desktop PC. The bridge ASIC connects the CPU bus with three different expansion busses, and it allows concurrent accesses from bus-masters on those busses to main memory. This paper describes a tool that was written as part of the verification project for just such an ASIC. This tool, called an ASIC mirror, provided cycle-for-cycle coherency checks for cycles and data for the CPU bus and all of the expansion busses connected to the bridge ASIC. Many of the checks provided by the ASIC mirror would have been virtually impossible to carry out by the use of self-checking stimulus alone. The architecture of the ASIC mirror and some examples of the bugs in the ASIC that were found by the mirror are discussed in this paper