Networked object oriented verification with C++ and Verilog

Verilog is a good language for modeling hardware, but it lacks a rich set of data structures that a verification engineer requires for verifying complex ASICs and systems. C++ provides a rich set of data structures but lacks support for modeling hardware. This paper discusses a tool which brings together these two languages, so hardware designers can model their hardware in Verilog and verification engineers can write their tests and test environments in C++