• DocumentCode
    3146383
  • Title

    Design consideration for reconfigurable processor DS-HIE — Trade-off between performance and chip area

  • Author

    Tanigawa, Kazuya ; Hironaka, Tetsuo

  • Author_Institution
    Grad. Sch. of Inf. Sci., Hiroshima City Univ., Hiroshima, Japan
  • fYear
    2011
  • fDate
    17-18 Nov. 2011
  • Firstpage
    187
  • Lastpage
    190
  • Abstract
    To develop a new processor for embedded applications, we must first characterize the processor, in order to take appropriate trade-off between performance and chip area. This study presents a DS-HIE architecture, which achieve high performance on a limited chip area by using the appropriate bit-width.
  • Keywords
    integrated circuit design; microprocessor chips; reconfigurable architectures; DS-HIE architecture; chip area; design consideration; embedded application; reconfigurable processor DS-HIE; digit-serial operation; reconfigurable processor;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SoC Design Conference (ISOCC), 2011 International
  • Conference_Location
    Jeju
  • Print_ISBN
    978-1-4577-0709-4
  • Electronic_ISBN
    978-1-4577-0710-0
  • Type

    conf

  • DOI
    10.1109/ISOCC.2011.6138679
  • Filename
    6138679
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3146383