Pure Ge mid-gap gate within an industrial high performance and low standby current 0.18 /spl mu/m CMOS process

Author

Alieu, J. ; Gwoziecki, R. ; Paoli, M. ; Skotnicki, T. ; Hernandez, C. ; Martin, F. ; Mourrain, C. ; Bensahel, D. ; Basso, M.-T. ; Galvier, J. ; Haond, M.

Author_Institution

CNET, Meylan, France

fYear

1998

fDate

9-11 June 1998

Firstpage

192

Lastpage

193

Abstract

For the first time, we demonstrate the feasibility of a Ge gate within an industrial 0.18 /spl mu/m CMOS process. The associated threshold voltage shift (/spl delta/V/sub th/) leads to an off-current (I/sub off/) reduction of as many as 6 decades. It is studied as a function of the Drain/Source anneal. No transconductance degradation is observed, which would not be the case if this shift was obtained by an increase in channel doping. In addition, we show that the SCE is well controlled and that Ge reduces the gate depletion.

Keywords

CMOS integrated circuits; annealing; elemental semiconductors; germanium; integrated circuit technology; 0.18 micron; CMOS process; Ge; Ge mid-gap gate; drain/source anneal; gate depletion; off-current; short channel effect; standby current; threshold voltage; transconductance; Annealing; Boron; CMOS process; Germanium silicon alloys; Ion implantation; MOS devices; Microelectronics; Silicon germanium; Telecommunications; Transconductance;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1998. Digest of Technical Papers. 1998 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-4770-6

Type

conf

DOI

10.1109/VLSIT.1998.689253

Filename

689253