Scan parallel loading in VHDL

A scan-based design can have several scan chains, and each scan chain can contain as many as 20,000 scan cells. During simulation, serial loading of scan values into a 20,000-element scan chain requires 20,000 clock cycles for each scan pattern. This loading operation adversely affects simulator performance and taxes simulator capacity. The capability within a simulator to load scan patterns directly into a scan chain by forcing the internal values of the scan elements would alleviate these problems and is badly needed. The VHDL language, unlike the Verilog language, does not provide the capability to force/assign a value to an internal signal in a design and cannot be used for parallel loading. This paper proposes a method to allow parallel scan loading in VHDL using a small set of the simulation command language (SSCL) to be supported by VHDL simulators