Rethinking processor instruction fetch: Inefficiencies-cracking mechanism

Identification of inefficiencies in some parts of conventional processor mechanism and its countermeasure are required in order to tackle conflicting design requirement in embedded system processors design. In this paper, we proposed a novel architecture which combines large entry of Instruction Register along with unique binary translation to aim more efficient fetch mechanism that leads to further reduction of processor´s code size. From simulation result, we found that the proposed method succeeded in reducing code size significantly compared to conventional processor.