Structured Design Verification: Function and Timing

Changes in the design verification environment brought about by VLSI design considerations are discussed. Multi-level modelling support is now required of efficient, interactive verification tools. The role of logic simulators in this environment is analyzed, especially in early error removal during the design cycle. A logic simulation system, which has been implemented as part of the IBM Design and Verification system, is described here. Particular attention is paid to the key areas of hierarchy in the design description, user interaction, and simulation speed.