STG timing extensions and simulation

Author

Goncharov, Michael V. ; Smirnov, Alexander B. ; Klotchkov, Ilya V. ; Starodoubtsev, A.

Author_Institution

Inst. of Anal. Instrum., Acad. of Sci., St. Petersburg, Russia

fYear

1998

fDate

16-19 Mar 1998

Firstpage

188

Lastpage

194

Abstract

The Signal Transition Graph (STG) model-a specification form that is widely used for asynchronous circuits´ behavior specification is extended to allow delay information specification. Timed STG models and their firing semantics are defined. Then the authors present an automatic technique for timed STG behavior specification in VHDL. The resulting VHDL specification may be used to simulate STG behavior with the specified delays. The requirements imposed on the STG to allow the joint environment-circuit behavior simulation are defined. Joint simulation of a circuit synthesized from STG with its environment is also presented

Keywords

Petri nets; asynchronous circuits; circuit analysis computing; delays; formal specification; hardware description languages; logic CAD; timing; STG timing extensions; STG timing simulation; Signal Transition Graph model; VHDL; VHDL specification; asynchronous circuit behavior specification; automatic technique; circuit behavior simulation; delay information specification; firing semantics; joint simulation; specification; timed STG behavior specification; timed STG models; Asynchronous circuits; Circuit simulation; Circuit synthesis; Concurrent computing; Delay; Information analysis; Instruments; Signal analysis; Signal synthesis; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Verilog HDL Conference and VHDL International Users Forum, 1998. IVC/VIUF. Proceedings., 1998 International

Conference_Location

Santa Clara, CA

ISSN

1085-9403

Print_ISBN

0-8186-8415-1

Type

conf

DOI

10.1109/IVC.1998.660700

Filename

660700