Design of timing-error-resilient systolic arrays for matrix multiplication

With semiconductor technology scaling, the size of transistors and their operating voltage keep decreasing. One of the major problems with advanced semiconductor technology is timing errors caused by process variation and noises. With such problem, conventional worst-case designs suffer poor system performance. This paper proposes aggressive designs of systolic arrays for matrix multiplication which can tolerate timing errors. When timing errors occur, the system reconfigures the computing cells with little performance degradation. Our implementation results show that our proposed designs achieve tolerance of timing errors with reasonable cost.