Time-interleaved sample clock generator for ultrasound beamformer application

A sample clock generator (SCG) for application in a 32-channel ultrasound receiver beamformer is proposed. The RX beamformer samples the echo signals at delayed timings to align them in the time domain before summing them. The proposed SCG employs a dual counter and comparator scheme to generate delayed sampling clocks with 4.17 ns delay control resolution. The SCG is implemented using Verilog RTL code and the analog block of the beamformer was modeled with ideal sample and hold circuits. The beamformer was simulated using a mixed-signal simulator and the results verify the feasibility of the proposed scheme.