DocumentCode :
3147220
Title :
Performance-effective compaction of standard cell library for edge-triggered latches utilizing 0.5 micron technology
Author :
Zhao, Chun ; Pan, W. ; Zhao, C.Z. ; Man, K.L. ; Choi, J. ; Chang, J.
Author_Institution :
Dept. of EEE, Univ. of Liverpool, Liverpool, UK
fYear :
2011
fDate :
17-18 Nov. 2011
Firstpage :
313
Lastpage :
316
Abstract :
Very-Large-Scale Integration (VLSI) is the process of establishing integrated circuits. Although the process is getting more and more complex, the development of VLSI has effectively increased the design capability and system performance. Power dissipation for large and complex circuits has always been a concern for engineers on the leading edge of technology. This paper aims at establishing a new standard cell library. Moreover, the most relevant definitions, classifications and details (including power and performance optimization) of the new standard cell library are presented in this paper.
Keywords :
VLSI; cellular arrays; circuit optimisation; flip-flops; integrated circuit design; logic design; VLSI; complex circuits; design capability; edge-triggered latches; integrated circuits; micron technology; performance optimization; performance-effective compaction; power dissipation; power optimization; standard cell library; system performance; very-large-scale integration; IC Design; LVS; Layout; Standard Cell Library;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
SoC Design Conference (ISOCC), 2011 International
Conference_Location :
Jeju
Print_ISBN :
978-1-4577-0709-4
Electronic_ISBN :
978-1-4577-0710-0
Type :
conf
DOI :
10.1109/ISOCC.2011.6138773
Filename :
6138773
Link To Document :
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