Design for testability in nano-CMOS analog integrated circuits using a new design analog checker

In this paper, we focus on safety-critical applications based on the System-on-Chip (SoC) approach design and using the nano-CMOS (Complementary Metal Oxide Semiconductor) technology. These systems are present in diverse areas in our life from consumer electronic products to automobile, aerospace, medical, nuclear and military applications. These products could cause injury or loss of human life if they fail or encounter errors. In fact, the malfunctioning of these equipments can be much dangerous which needs special attention to ensure the functionality, quality and dependability of the product. Thus, dependability must be considered from the beginning when designing the system. Therefore, testing should even be considered earlier, intertwined with the design process. The process of designing for better testability is called design for testability (DfT). The first part of the paper presents a DfT technique using a new design analog checker circuit to assure the detection of defects occurring in nano-CMOS analog integrated circuits (ICs). The checker is implemented in full-custom 65nm CMOS technology at 1 V power supply. SPICE simulations of the post-layout extracted CMOS checker, which includes all parasitic, are used to validate the technique and demonstrate the acceptable electrical behaviour of the checke.