DocumentCode
3147520
Title
Low area and high speed SHA-1 implementation
Author
Jung, Eun-Gu ; Han, Daewan ; Lee, Jeong-Gun
Author_Institution
Attached Inst., ETRI, Daejeon, South Korea
fYear
2011
fDate
17-18 Nov. 2011
Firstpage
365
Lastpage
367
Abstract
In this paper, a low area and high speed SHA-1 implementation with multi-input addition based on a carry-save adder is proposed. Compared with the fastest SHA-1 design up to date, our implementation reduces the area by 24.5% as well as increases the speed by 13.6%. When the proposed scheme keeps the same clock frequency as the counterpart, it decreases the area by 39.7% further.
Keywords
adders; clocks; SHA-1 implementation; carry-save adder; clock frequency; multi-input addition; SHA-1; carry-save adder; high speed; low area;
fLanguage
English
Publisher
ieee
Conference_Titel
SoC Design Conference (ISOCC), 2011 International
Conference_Location
Jeju
Print_ISBN
978-1-4577-0709-4
Electronic_ISBN
978-1-4577-0710-0
Type
conf
DOI
10.1109/ISOCC.2011.6138786
Filename
6138786
Link To Document