DocumentCode
3147672
Title
Optimum Reduction of Programmable Logic Array
Author
Hu, T.C. ; Kuo, Y.S.
Author_Institution
Department of Electrical Engineering and Computer Sciences, University of California, San Diego, La Jolla, CA
fYear
1983
fDate
27-29 June 1983
Firstpage
553
Lastpage
558
Abstract
We consider the optimum PLA column folding problem where vertices in the column intersection graph are first partitioned into two parts. Both upper and lower bounds on the size of the folding are given in terms of the number of edges and vertices in the bipartite graph G. Efficient polynomial optimum algorithms are given for the case that G is a tree and other cases. A heuristic algorithm with error bound is given for a general bipartite graph. A new graph model is introduced. We also study one-cut bipartite folding, AND-OR-AND row folding, and the general partitioning problem.
Keywords
Bipartite graph; Combinational circuits; Logic arrays; Logic functions; Partitioning algorithms; Polynomials; Programmable logic arrays; Sparse matrices; Sufficient conditions; Tree graphs;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation, 1983. 20th Conference on
ISSN
0738-100X
Print_ISBN
0-8186-0026-8
Type
conf
DOI
10.1109/DAC.1983.1585707
Filename
1585707
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