DocumentCode
3147904
Title
A new STI process based on selective oxide deposition [for CMOS logic]
Author
Elbel, N. ; Gabric, Z. ; Langheinrich, W. ; Neureither, B.
Author_Institution
Semicond. Group, Siemens AG, Munich, Germany
fYear
1998
fDate
9-11 June 1998
Firstpage
208
Lastpage
209
Abstract
A new shallow trench isolation (STI) process with a planarization concept based on a selective oxide deposition (SELOX) is presented. Different oxide growth rates on pad nitride and silicon result in good global planarity after the trench fill process. The straightforward concept of the SELOX process requires a minimum of process steps, making it particularly interesting for cost and throughput optimization in manufacturing. Electrical parameters are comparable to those achieved with common STI processes.
Keywords
CMOS logic circuits; VLSI; chemical vapour deposition; isolation technology; STI process; electrical parameters; global planarity; oxide growth rates; pad nitride; planarization concept; process steps; selective oxide deposition; shallow trench isolation; throughput optimization; trench fill process; Chemical technology; Chemical vapor deposition; Cost function; Etching; Isolation technology; Manufacturing processes; Performance loss; Planarization; Silicon; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, 1998. Digest of Technical Papers. 1998 Symposium on
Conference_Location
Honolulu, HI, USA
Print_ISBN
0-7803-4770-6
Type
conf
DOI
10.1109/VLSIT.1998.689259
Filename
689259
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