Automatic Routing of Double Layer Gate Arrays Using a Moving Cursor

This paper presents an efficient algorithm for routing of the interconnections on a large gate array layout. The algorithm employs a vertical cursor strip that traverses the chip in a single pass, laying horizontal segments in its wake on one layer, and vertical segments within the cursor itself, generally on the other layer. The routing algorithm presented here was developed as part of the UK5000 design automation system for large gate arrays and was written in standard FORTRAN 77. Routing results are presented for two gate array layouts.