Title :
A shallow trench isolation with SiN guard-ring for sub-quarter micron CMOS technologies
Author :
Ogura, T. ; Yamamoto, T. ; Saito, Y. ; Hayashi, Y. ; Mogami, T.
Author_Institution :
Silicon Syst. Res. Labs., NEC Corp., Kanagawa, Japan
Abstract :
Shallow trench isolation (STI) technology is important to realize high-speed and high-packing-density CMOS-LSIs. A new SiN guard-ring on the upper edge of filled SiO/sub 2/ for steep-sidewall STI is proposed and evaluated to improve the reverse narrow channel effect and device reliability. Good isolation characteristics and sufficient improvement of the reverse narrow channel effect are achieved for STI with SiN guard-ring structure.
Keywords :
CMOS integrated circuits; high-speed integrated circuits; integrated circuit reliability; isolation technology; SiN-SiO/sub 2/; device reliability; guard-ring; high-speed ICs; isolation characteristics; packing density; reverse narrow channel effect; shallow trench isolation; steep-sidewall STI; sub-quarter micron CMOS; CMOS technology; Capacitors; Fabrication; Filling; Isolation technology; MOSFET circuits; Oxidation; Planarization; Silicon compounds; Wet etching;
Conference_Titel :
VLSI Technology, 1998. Digest of Technical Papers. 1998 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-4770-6
DOI :
10.1109/VLSIT.1998.689260
