A Design Verification Methodology Based on Concurrent Simulation and Clock Suppression

This paper outlines a methodology for design verification of very large networks based on Concurrent Simulation and Clock Suppression. Concurrent Simulation is expected to yield a 30:1 to 600:1 speed advantage over conventional (serial) simulation when roughly 5,000 "good machines" are simulated concurrently. This speed advantage increases with the number of concurrent machines. Clock Suppression is an auxiliary technique to avoid simulation slowdowns if very large networks with very large clock fanouts must be simulated. The methodology proposed here for design verification is "Concurrent Case Simulation", i.e., the simultaneous simulation of distinct sets of input patterns. Advantages of this method are (1) speed, (2) the fundamental ability to simulate cases concurrently, (3) to observe differences between cases in a more economic, simpler, and more natural style than with serial simulation, (4) to run many more cases than would be possible with serial simulation, (5) and the fact that running cases against each other establishes a powerful design verification philosophy.