Consistency Checking for MOS/VLSI Circuits

A general algorithm is presented for consistency checking between schematics. A transistor level schematic is partitioned into functional blocks by tracing direct current paths. The first level consistency check is performed on the directed graphs constructed from these functional blocks. A recursive, graph matching algorithm is introduced to find signal correspondences in the functional blocks. The second level check is performed within the functional blocks for either identical component connectivity or logic equivalence. Performance of the program is demonstrated using an NMOS chip.