Design, simulation, and evaluation of a SEP-hard SRAM memory cell

The authors describe the design, simulation, and evaluation of a six-transistor CMOS memory cell for a 64K SEP-hard SRAM. A technique for SPICE simulation of the memory cell which allows the determination of the effective critical charge in the cell is given. The critical charge data, along with the physical dimensions of the cell, are then used to calculate the single-event upset rate. SEP measurements performed using heavy ions are correlated to the simulations of the memory cell as a function of the resistor value. The UTMC 64K SRAM demonstrates an SEP error rate less than 1.0E-10 errors/bit-day for a 90% worst-case geosynchronous orbit environment. This error rate is obtained over the entire -55°C to +125°C temperature range while maintaining less than 55 ns read/write cycle time