Fast design space exploration for MPSoC architectures

Design space of a system on chip (SoC) with multiple processor cores (MPSoC) is huge, and its architecture exploration is very time consuming. Trace driven simulations can accelerate the exploration effectively and various traces have been proposed to reuse some simulation results of one configuration for others with similar parameters. However, the traces are not independent, and each of them has different generation and access overheads. This paper presents a framework to describe the relationships of various traces in an MPSoC, where a simple time estimator is provided to select traces that minimize the overall exploration time. In our experiments, 2~3 order speedup can be simply achieved once the traces are appropriately chosen.