Title :
Stacked gate dielectrics with TaO for future CMOS technologies
Author :
Kizilyaili, I.C. ; Roy, P.K. ; Baumann, F. ; Huang, R.Y. ; Hwang, D. ; Chacon, C. ; Irwin, R. ; Ma, Y. ; Alers, G.
Author_Institution :
Bell Labs., Lucent Technol., Orlando, FL, USA
Abstract :
Advances in lithography and thinner SiO/sub 2/ gate oxides have enabled the scaling of MOS (metal-oxide-semiconductor) technologies to sub-0.25 μm feature size. High dielectric constant materials, such as Ta/sub 2/O/sub 5/, have been suggested as a substitute for SiO/sub 2/ as the gate material beyond t/sub ox/=25 Å. However, the Si-Ta/sub 2/O/sub 5/ material system suffers from unacceptable levels of bulk fixed charge, high density of interface trap states, and low silicon interface carrier mobility. We present a solution to these issues through the synthesis of a SiO/sub 2/-Ta/sub 2/O/sub 5/-SiO/sub 2/ stacked dielectric. The fabricated transistors exhibit excellent I-V characteristics.
Keywords :
CMOS integrated circuits; carrier mobility; dielectric thin films; integrated circuit technology; silicon compounds; tantalum compounds; 0.25 micron; 25 A; CMOS technologies; I-V characteristics; SiO/sub 2/-Ta/sub 2/O/sub 5/-SiO/sub 2/; Ta/sub 2/O/sub 5/ dielectric film; carrier mobility; high dielectric constant material; interface trap states; stacked gate dielectrics; CMOS technology; Capacitance-voltage characteristics; Dielectric materials; Dielectric measurements; Dielectric substrates; High-K gate dielectrics; MOSFETs; Material storage; Silicon; Tunneling;
Conference_Titel :
VLSI Technology, 1998. Digest of Technical Papers. 1998 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-4770-6
DOI :
10.1109/VLSIT.1998.689262
