Advanced Clockgating Schemes for Fused-Multiply-Add-Type Floating-Point Units

Author

Preiss, Jochen ; Boersma, Maarten ; Mueller, Silvia Melitta

Author_Institution

IBM Deutschland R&D GmbH, Boeblingen, Germany

fYear

2009

fDate

8-10 June 2009

Firstpage

48

Lastpage

56

Abstract

The paper introduces fine-grain clockgating schemes for fused multiply-add-type floating-point units (FPU). The clockgating is based on instruction type, precision and operand values. The presented schemes focus on reducing the power at peak performance, where each FPU stage is used in nearly every cycle and conventional schemes have little impact on the power consumption. Depending on the instruction mix, the schemes allow to turn off 18% to 74%of the register bits. Even for the worst case instruction 18% to 37% of the FPU are shut down depending on the data patterns.

Keywords

adders; clocks; floating point arithmetic; logic gates; low-power electronics; multiplying circuits; advanced clockgating schemes; fine-grain clockgating schemes; fused-multiply-add-type floating-point units; instruction type; operand values; power consumption; register bits; Clocks; Cooling; Digital arithmetic; Energy consumption; Hardware; Logic; Pipelines; Registers; Research and development; Supercomputers; IEEE 754 Standard; clockgating; floating-point hardware; fused multiply-add; power reduction;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Arithmetic, 2009. ARITH 2009. 19th IEEE Symposium on

Conference_Location

Portland, OR

ISSN

1063-6889

Print_ISBN

978-0-7695-3670-5

Type

conf

DOI

10.1109/ARITH.2009.17

Filename

5223359