Unified Approach to the Design of Modulo-(2^n +/- 1) Adders Based on Signed-LSB Representation of Residues

Moduli of the form 2ⁿ plusmn 1, which greatly simplify certain arithmetic operations in residue number systems (RNS), have been of longstanding interest. A steady stream of designs for modulo (2ⁿ plusmn 1) adders has rendered the latency of such adders quite competitive with ordinary adders. The next logical step is to approach the problem in a unified and systematic manner that does not require each design to be taken up from scratch and to undergo the error prone and labor intensive optimization for high speed and low power dissipation. Accordingly, we devise a new redundant representation of mod (2ⁿ plusmn 1) residues that allows ordinary fast adders and a small amount of peripheral logic to be used for mod (2ⁿ plusmn 1) addition. Advantages of the building block approach include shorter design time, easier exploration of the design space (area, speed, power tradeoffs), and greater confidence in the correctness of the resulting circuits. Advantages of the unified design include the possibility of fault tolerant and gracefully degrading RNS circuit realizations with fairly low hardware redundancy.